AD9753 |
RFQ for AD9753 Required Field |
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| Technical/Catalog Information | AD9753AST |
| Vendor | Analog Devices Inc |
| Category | Integrated Circuits (ICs) |
| Data Interface | Parallel |
| Number of Bits | 12 |
| Operating Temperature | -40°C ~ 85°C |
| Package / Case | 48-LQFP |
| Packaging | Tray |
| Voltage Supply Source | Analog and Digital |
| Settling Time | 11ns |
| RoHS Status | RoHS Non-Compliant |
| Other Names | AD9753AST AD9753AST |
| Product | Manufacturers | Pack | D/C |
| AD9753 | Analog Devices | new | - |
The AD9753 is a dual, muxed port, ultrahigh-speed, single-channel, 12-bit CMOS DAC. It integrates a high-quality 12-bit TxDAC+core, a voltage reference, and digital interface circuitry into a small 48-lead LQFP package. The AD9753 offers excep-tional ac and dc performance while supporting update rates up to 300 MSPS.
The AD9753 has been optimized for ultrahigh-speed applica-tions up to 300 MSPS where data rates exceed those possible on a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches can be time multiplexed to the high-speed DAC in several ways. This PLL drives the DAC latch at twice the speed of the exter-
nally applied clock and is able to interleave the data from the two input channels. The resulting output data rate is twice that of the two input channels. With the PLL disabled, an external
2* clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK) can be driven either differen-tially or single-endedly, with a signal swing as low as 1 V p-p.
Typical Application |
Features |
| Communications: LMDS, LMCS, MMDSBase StationsDigital SynthesisQAM and OFDM | 12-Bit Dual Muxed Port DAC300 MSPS Output Update RateExcellent SFDR and IMD PerformanceSFDR to Nyquist @ 25 MHz Output: 69 dBInternal Clock Doubling PLLDifferential or Single-Ended Clock InputOn-Chip 1.2 V ReferenceSingle 3.3 V Supply OperationPower Dissipation: 155 mW @ 3.3 V48-Lead LQFP |
| Parameter | With Respectto | Min | Max | Unit |
| AVDD, DVDD, CLKVDD, PLLVDD AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM REFIO, REFLO, FSADJ IOUTA, IOUTB Digital Data Inputs (DB13 to DB0) CLK+/CLK, PLLLOCK DIV0, DIV1, RESET LPF Junction Temperature Storage Temperature Lead Temperature (10 sec) |
ACOM, DCOM, CLKCOM, PLLCOM ACOM, DCOM, CLKCOM, PLLCOM ACOM, DCOM, CLKCOM, PLLCOM ACOM ACOM DCOM CLKCOM CLKCOM PLLCOM |
0.3 65 |
+3.9 +3.9 +3.9 AVDD + 0.3 AVDD + 0.3 DVDD + 0.3 CLKVDD + 0.3 CLKVDD + 0.3 PLLVDD + 0.3 150 +150 300 |
V V V V V V V V V °C °C °C |
